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How to run AFU and ASE.pdf 0 → 100644
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Master_s_Thesis_2019.pdf 0 → 100644
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The_Full_State_Simulator_(BP_and_Cache)/READ_ME.sh 0 → 100644
# =====================================================================
# Konstantinos Kyriakidis,
# Electrical and Computer Engineering, Technical University of Crete,
# kkyriakidis@mhl.tuc.gr
#
# HOW TO RUN AN AFU SYNTHESIS AND DOWNLOAD
# =====================================================================
// ====================================================================
// GENERAL
// ====================================================================
1.
// Locate common_include.mk file. It contains the sw build rules.
// It is necessary and will be used by the SW Makefile.
// You can copy it in the sw directory for simplicity.
2.
// All trace files are zipped. To execute the SW, first unzip the
// trace files that you wish to have as inputs. Using a different trace file,
// means that you should probably also alter the appropriate code section
// inside the full_system.c SW API.
3.
// int32_cache_trace_converter.c and int64_bp_trace_converter.c are
// custom applications that were used to alter the stracture of input
// trace files, more specifically the format of an input trace line.
// For example: binary line-format to a single 64-bit integer.
// They are located in the sw directory.
4.
// Take a look at the hw_make.sh and hw_make_sim.sh scripts that are
// developed to simplify and speed-up the build process for ASE simulation.
// They are located in the hw directory.
5.
// Take a look at the sw.sh script, developed to simplify and speed-up
// the SW execution process for ASE simulation. It located in the sw directory.
6.
// Use the MSc Thesis and the Guide provided :)
7.
// gbs_and_logs.zip includes a working green bitstream for the
// Full State Simulator (view MSc Thesis) and also the key .log
// and .rpt files that were exported during the bistream synthesis.
8.
// read_from_txt_char_to_64bitint.c is a helper application that reads
// lines from a binary .txt directly as 64-bit integers.
// It located in the sw directory.
// ====================================================================
// AFU Hardware DOWNLOAD
// ====================================================================
// 1st step: connect to vLabs and setup the environment
// ====================================================================
ssh kyriakidd@ssh-iam.intel-research.net
// 2nd step: Build the green bitstream !!!
// ====================================================================
source /export/fpga/bin/setup-fpga-env fpga-bdx-opae
cd /homes/kyriakidd/0_full_system/hw
rm -rf build_fpga
# Configure a Quartus build area
afu_synth_setup -s rtl/sources.txt build_fpga
cd build_fpga
# Run Quartus in the vLab batch queue
qsub-synth
# Monitor the build (the file is created after the job starts)
tail -f build.log
// 3rd step: Load the .gbs to the FPGA and run the SW
// ====================================================================
source /export/fpga/bin/setup-fpga-env fpga-bdx-opae
# Open a shell on an FPGA system of the configured class
qsub-fpga
export PBS_O_WORKDIR=/homes/kyriakidd/0_full_system/hw/build_fpga
# Go to the directory whree qsub-synth was run above
cd $PBS_O_WORKDIR
# Load the image onto an FPGA
fpgaconf full_system.gbs
# Compile the matching software
cd ../../sw
make
# Run the program
./full_system 14361067 262144 10000000 32 1024 4 1024
// ====================================================================
// Simulating designs with ASE
// ====================================================================
source /export/fpga/bin/setup-fpga-env fpga-bdx-opae
qsub-sim
# Go to the same path as the intel-fpga-bbb example above
cd /homes/kyriakidd/0_full_system/hw
# Construct a simulation build directory
rm -rf build_sim/
afu_sim_setup -s rtl/sources.txt build_sim
# Split the screen (or use 2 terinals)
tmux
^b%
# switch between screens
^bo
# Compile and run the RTL simulator
cd build_sim
make
make sim
# Switch to the other (software) pane
^bo
# Copy the export ASE_WORKDIR=<path> from the RTL simulator pane and invoke it here
export ASE_WORKDIR=/homes/kyriakidd/0_full_system/hw/build_sim/work
cd ../sw
make
with_ase ./full_system 2000 256 2000 32 1024 4 1024
The_Full_State_Simulator_(BP_and_Cache)/hw/hw_make.sh 0 → 100755
# =====================================================================
# Konstantinos Kyriakidis,
# Electrical and Computer Engineering, Technical University of Crete,
# kkyriakidis@mhl.tuc.gr
#
# -- HW make bash script --
# =====================================================================
#!/bin/bash
rm -rf build_sim
afu_sim_setup --source rtl/sources.txt build_sim
(cd build_sim && make)
The_Full_State_Simulator_(BP_and_Cache)/hw/hw_make_sim.sh 0 → 100755
# =====================================================================
# Konstantinos Kyriakidis,
# Electrical and Computer Engineering, Technical University of Crete,
# kkyriakidis@mhl.tuc.gr
#
# -- HW Sim execution bash script --
# =====================================================================
#!/bin/bash
(cd build_sim && make sim)
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/afu_fifo.v 0 → 100644
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module afu_fifo_fifo_160_6sdoz6y (
clock,
data,
rdreq,
sclr,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input clock;
input [511:0] data;
input rdreq;
input sclr;
input wrreq;
output almost_full;
output empty;
output full;
output [511:0] q;
output [3:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [511:0] sub_wire3;
wire [3:0] sub_wire4;
wire almost_full = sub_wire0;
wire empty = sub_wire1;
wire full = sub_wire2;
wire [511:0] q = sub_wire3[511:0];
wire [3:0] usedw = sub_wire4[3:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.almost_full (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.usedw (sub_wire4),
.aclr (),
.almost_empty (),
.eccstatus ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 12,
scfifo_component.enable_ecc = "FALSE",
scfifo_component.intended_device_family = "Arria 10",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 512,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/bht_memory.sv 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// Branch History Table Memory Module
// =====================================================================
`include "branch_header.vh"
`timescale 1 ps / 1 ps
import branch_package::*;
module bht_memory(
address,
clock,
data,
rden,
wren,
q);
input [IDX_SIZE-1:0] address;
input clock;
input [N_BIT-1:0] data;
input rden;
input wren;
output [N_BIT-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [N_BIT-1:0] sub_wire0;
wire [N_BIT-1:0] q = sub_wire0[N_BIT-1:0];
altera_syncram altera_syncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus ( ),
.q_b ( ),
.rden_b (1'b1),
.sclr (1'b0),
.wren_b (1'b0));
defparam
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = MEM_DEPTH, // MEM_DEPTH = (2**IDX_SIZE);
altera_syncram_component.operation_mode = "SINGLE_PORT",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_a = "UNREGISTERED",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_port_a = "DONT_CARE",
altera_syncram_component.widthad_a = IDX_SIZE, // address width
altera_syncram_component.width_a = N_BIT; // entire memory line width
endmodule // bht_memory
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/branch_header.vh 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// Branch Predictor Header File
// =====================================================================
`ifndef BRANCH_PACKAGE_VH
`define BRANCH_PACKAGE_VH
package branch_package;
// *****************************************
// general parameters
// *****************************************
parameter PC_SIZE = 32; // pc lenght
parameter OP_SIZE = 5; // op-code lenght
parameter IDX_SIZE = 10;
parameter MEM_DEPTH = (2**IDX_SIZE); // # of memlines in BTB, BHT and META
parameter BTB_SIZE = OP_SIZE + PC_SIZE; // BTB memline lenght
parameter TRACE_LINE_LENGTH = PC_SIZE + PC_SIZE + 1 + OP_SIZE; // single trace file line
// *****************************************
// parameters for the simple n-bit predictor
// *****************************************
parameter N_BIT = 2; // size of the n-bit BHT predictor
// *****************************************
// parameters for the PAP
// *****************************************
parameter GAP = 0; // '1' if the user wants a single global shift register
parameter SR_SIZE = 10; // bit-width of the shift register.
parameter SR_IDX = 2; // bits from the PC that index the SR memory
parameter N = (2**SR_IDX); // # of shift registers
parameter PHT_MEM_DEPTH = (2**SR_SIZE); // PHT memory depth
parameter K_BIT = 2; // bit-width of the k-bit PHT.
// *****************************************
// parameters for the selector s-bit predictor
// *****************************************
parameter S_BIT = 2; // size of the n-bit BHT predictor
endpackage
`endif
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/btb_memory.sv 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// Branch Target Buffer Memory Module
// =====================================================================
`include "branch_header.vh"
`timescale 1 ps / 1 ps
import branch_package::*;
module btb_memory(
address,
clock,
data,
rden,
wren,
q);
input [IDX_SIZE-1:0] address;
input clock;
input [BTB_SIZE-1:0] data;
input rden;
input wren;
output [BTB_SIZE-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [BTB_SIZE-1:0] sub_wire0;
wire [BTB_SIZE-1:0] q = sub_wire0[BTB_SIZE-1:0];
altera_syncram altera_syncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus ( ),
.q_b ( ),
.rden_b (1'b1),
.sclr (1'b0),
.wren_b (1'b0));
defparam
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = MEM_DEPTH, // MEM_DEPTH = (2**IDX_SIZE);
altera_syncram_component.operation_mode = "SINGLE_PORT",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_a = "UNREGISTERED",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_port_a = "DONT_CARE",
altera_syncram_component.widthad_a = IDX_SIZE, // address width
altera_syncram_component.width_a = BTB_SIZE; // entire memory line width
endmodule // btb_memory
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/cache_types_package.vh 0 → 100755
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.
//
// --- Cache module header file ---
// =====================================================================
`ifndef CACHE_TYPES_PACKAGE_VH
`define CACHE_TYPES_PACKAGE_VH
package cache_types_package;
// 0 for MRU
// 1 for LRU <----------- mainly
parameter MRU_OR_LRU = 1;
// 0 for Write Back <--- mainly
// 1 for Write Through
parameter WRB_OR_WRT = 0;
parameter WAYS = 4; // cache set-associativity
parameter DTAG_W = 22; // tag size
parameter DIDX_W = 5; // index size
// Cache SIZE (Depth)
// gia cache frame ligotero apo 32 den 8a leitourgei ($bits(dcache_frame)/32)+1
parameter SIZE = (2**DIDX_W);
parameter ADDR_W = DTAG_W+DIDX_W;
parameter RPL_IDX_SIZE = $clog2(WAYS);
typedef logic [DIDX_W-1:0] addr_t; // cache address size.
typedef logic [ADDR_W-1:0] addr_size; // size of a cache-way.
typedef struct packed {
logic v; // shows if a set has a valid tag
logic dirty; // shows if a set is dirty
logic [DTAG_W - 1:0] tag; // tag
logic [RPL_IDX_SIZE-1:0] replacement_index; // each set has its own replacement index (Mainly used for LRU uptates)
} dcache_entry; //single cache way
typedef struct packed {
dcache_entry [WAYS - 1:0] set; // number of sets equals to number of cache-ways
logic [RPL_IDX_SIZE - 1:0] most; // indicates the most recently used set
logic [RPL_IDX_SIZE - 1:0] least; // indicates the least recently used set
} dcache_frame; //an entire cacheline
typedef struct packed {
logic [DTAG_W - 1:0] tag; // address dag
logic [DIDX_W - 1:0] idx; // address index
} dcachef_t; // address from "outside" :)
endpackage
`endif
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/full_system.json 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
// --- The .json file ---
// =====================================================================
{
"version": 1,
"platform-name" : "HARP",
"afu-image": {
"magic-no": 488605312,
"interface-uuid": "00000000-0000-0000-0000-000000000000",
"clock-frequency-low": "auto",
"clock-frequency-high": "auto",
"power": 0,
"afu-top-interface":
{
"class": "ccip_std_afu",
"module-ports" :
[
{
"class": "cci-p",
"params":
{
"clock": "pClkDiv2"
}
}
]
},
"accelerator-clusters":
[
{
"name": "nbit",
"total-contexts": 1,
"accelerator-type-uuid": "4634522f-0d1f-4fd3-983f-8fb7c50b552d"
}
]
}
}
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/full_system_afu.sv 0 → 100644
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The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/n_bit_without_btb.sv 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// n-bit Branch Predictor without BTB
// =====================================================================
`include "branch_header.vh"
`include "bht_memory.sv"
import branch_package::*;
// &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
// ------------------------------------------------------------------------ top level
module n_bit_without_btb(
input logic CLK,
input logic nRST,
input logic valid_request, // signals if this is a valid request to the BP
input logic [PC_SIZE-1:0] pc, // current PC
input logic [OP_SIZE-1:0] branch_type, // branch type-opcode
input logic taken, // taken or not taken branch
output logic bimod_pred, // '1=taken' or '0=not-taken'
output logic bht_prediction, // '1=hit' or '0=miss'
// state
output logic [IDX_SIZE-1:0] state_nbit_without_address,
output logic [N_BIT-1:0] state_nbit_without_data
);
logic bht_mem_ren;
logic bht_mem_wen;
logic [IDX_SIZE-1:0] bht_indexed_address;
logic [N_BIT-1:0] previous_prediction;
logic [N_BIT-1:0] new_prediction;
bp_control_without bpc_without(
// bp control
.CLK,
.nRST,
.valid_request,
.pc,
.branch_type,
.taken,
.bimod_pred,
.bht_prediction,
// BHT memory signals
.bht_address(bht_indexed_address),
.bht_data(new_prediction),
.bht_rden(bht_mem_ren),
.bht_wren(bht_mem_wen),
.bht_q(previous_prediction),
.state_nbit_without_address,
.state_nbit_without_data
);
bht_memory bht_mem_3(
.address(bht_indexed_address),
.clock(CLK),
.data(new_prediction),
.rden(bht_mem_ren),
.wren(bht_mem_wen),
.q(previous_prediction)
);
endmodule //n_bit_without_btb
// &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
// ----------------------------------------------------------------------- bp control
module bp_control_without(
// Top level signals
input logic CLK,
input logic nRST,
input logic valid_request, // signals if this is a valid request to the BP
input logic [PC_SIZE-1:0] pc, // current PC
input logic [OP_SIZE-1:0] branch_type, // branch type-opcode
input logic taken, // taken or not taken branch
output logic bht_prediction, // '1=hit' or '0=miss'
output logic bimod_pred, // '1=taken' or '0=not-taken'
// BHT memory signals
output logic [IDX_SIZE-1:0] bht_address, // BHT address request
output logic [N_BIT-1:0] bht_data, // memline to BHT
output logic bht_rden, // BHT REN
output logic bht_wren, // BHT WEN
input logic [N_BIT-1:0] bht_q, // BHT memline out
// state
output logic [IDX_SIZE-1:0] state_nbit_without_address,
output logic [N_BIT-1:0] state_nbit_without_data
);
logic [OP_SIZE-1:0] op;
logic [IDX_SIZE-1:0] update_address;
logic taken_not_taken;
typedef enum logic [1:0] {FETCH, WAIT, COMPARE_AND_UPDATE} state_type;
state_type state, next_state;
//--------------------------------------------------- control FSM sequential
always_ff @(posedge CLK, negedge nRST)
begin
if(~nRST) begin
state <= FETCH;
end
else begin
state <= next_state;
end
end
//--------------------------------------------------- control FSM combinational
always_comb
begin
// --------------------------------------- cases
casez(state)
FETCH:
begin
if(valid_request)begin
next_state = WAIT;
end
else begin
next_state = FETCH;
end
end
WAIT:
begin
next_state = COMPARE_AND_UPDATE;
end
COMPARE_AND_UPDATE:
begin
next_state = FETCH;
end
default: next_state = FETCH;
endcase
end
always_ff @(posedge CLK)
begin
// --------------------------------------- cases
casez(state)
FETCH:
begin
// state
state_nbit_without_address <= 0;
state_nbit_without_data <= 0;
// reset predictions
bht_prediction <= 0;
// reset bht values
bht_data <= 0;
bht_wren <= 0;
bimod_pred <= 0;
// start if request is valid
if(valid_request)begin
bht_rden <= 1;
bht_address <= (pc>>19)^(pc>>3); // BTH address
update_address <= (pc>>19)^(pc>>3); // store the address for the next state in order to update
taken_not_taken <= taken; // store this information to compare in the next state
op <= branch_type;
end
else begin
bht_rden <= 0;
bht_address <= 0;
update_address <= 0;
taken_not_taken <= 0;
op <= 0;
end
end
WAIT:
begin
// state
state_nbit_without_address <= 0;
state_nbit_without_data <= 0;
//
update_address <= update_address;
taken_not_taken <= taken_not_taken;
op <= op;
bimod_pred <= 0;
//
bht_rden <= 0;
bht_wren <= 0;
bht_address <= 0;
bht_prediction <= 0;
bht_data <= 0;
end
COMPARE_AND_UPDATE:
begin
// -------------------------------------------------------- preventing gated clocks
update_address <= update_address;
taken_not_taken <= taken_not_taken;
op <= op;
// state
state_nbit_without_address <= update_address;
// --------------------------------------------------------
// inform about a t/nt
if(op==2 | op==3 | op==4 | op==5) begin
// always taken
bimod_pred <= 1;
end
else begin
// bht prediction t/nt
bimod_pred <= bht_q[N_BIT-1];
end
// update the BHT
bht_rden <= 0;
bht_wren <= 1;
bht_address <= update_address;
// ------------------------------------------------------------------------ start comparing in order to update bht
// case 0: Jumps are always taken
if(op==2 | op==3 | op==4 | op==5) begin
// allways predict taken correctly
bht_prediction <= 1;
// in case of a jr we and no RAS we update the BHT
bht_data <= bht_q;
state_nbit_without_data <= bht_q;
end
// ------------------------------------------------------------------- case 1: prediction == not taken (all zeros) / case == not taken.
else if((bht_q == {N_BIT{1'b0}}) & !taken_not_taken) begin
bht_prediction <= 1;
// bht stays the same
bht_data <= bht_q;
state_nbit_without_data <= bht_q;
end
// ------------------------------------------------------------------- case 2: prediction == not taken (MSB==0) / case == not taken
else if((bht_q[N_BIT-1] == 0) & !taken_not_taken) begin
bht_prediction <= 1;
bht_data <= bht_q - 1;
state_nbit_without_data <= bht_q - 1;
end
// ------------------------------------------------------------------- case 3: prediction == not taken (MSB==0) / case == taken
else if((bht_q[N_BIT-1] == 0) & taken_not_taken) begin
bht_prediction <= 0;
bht_data <= bht_q + 1;
state_nbit_without_data <= bht_q + 1;
end
// ------------------------------------------------------------------- case 4: prediction == taken (all ones) / case == taken
else if((bht_q == {N_BIT{1'b1}}) & taken_not_taken) begin
bht_prediction <= 1;
// bht stays the same
bht_data <= bht_q;
state_nbit_without_data <= bht_q;
end
// ------------------------------------------------------------------- case 5: prediction == taken (MSB==1) / case == taken
else if((bht_q[N_BIT-1] == 1) & taken_not_taken) begin
bht_prediction <= 1;
bht_data <= bht_q + 1;
state_nbit_without_data <= bht_q + 1;
end
// ------------------------------------------------------------------- case 6: prediction == taken (MSB==1) / case == not taken
else begin
bht_prediction <= 0;
bht_data <= bht_q - 1;
state_nbit_without_data <= bht_q - 1;
end
end
default:
begin
// state
state_nbit_without_address <= 0;
state_nbit_without_data <= 0;
//
update_address <= 0;
taken_not_taken <= 0;
op <= 0;
bimod_pred <= 0;
//
bht_rden <= 0;
bht_wren <= 0;
bht_address <= 0;
bht_prediction <= 0;
bht_data <= 0;
end
endcase
end
endmodule // bp_control
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/pht_memory.sv 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// Pattern History Table Memory Module
// =====================================================================
`include "branch_header.vh"
`timescale 1 ps / 1 ps
import branch_package::*;
module pht_memory(
address,
clock,
data,
rden,
wren,
q);
input [SR_SIZE-1:0] address;
input clock;
input [K_BIT-1:0] data;
input rden;
input wren;
output [K_BIT-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [K_BIT-1:0] sub_wire0;
wire [K_BIT-1:0] q = sub_wire0[K_BIT-1:0];
altera_syncram altera_syncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus ( ),
.q_b ( ),
.rden_b (1'b1),
.sclr (1'b0),
.wren_b (1'b0));
defparam
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = PHT_MEM_DEPTH, // PHT_MEM_DEPTH = (2**SR_SIZE);
altera_syncram_component.operation_mode = "SINGLE_PORT",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_a = "UNREGISTERED",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_port_a = "DONT_CARE",
altera_syncram_component.widthad_a = SR_SIZE, // address width
altera_syncram_component.width_a = K_BIT; // entire memory line width
endmodule // pht_memory
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/selector_memory.sv 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// Selector Predictor Memory Module
// =====================================================================
`include "branch_header.vh"
`timescale 1 ps / 1 ps
import branch_package::*;
module selector_memory(
address,
clock,
data,
rden,
wren,
q);
input [IDX_SIZE-1:0] address;
input clock;
input [S_BIT-1:0] data;
input rden;
input wren;
output [S_BIT-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [S_BIT-1:0] sub_wire0;
wire [S_BIT-1:0] q = sub_wire0[S_BIT-1:0];
altera_syncram altera_syncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus ( ),
.q_b ( ),
.rden_b (1'b1),
.sclr (1'b0),
.wren_b (1'b0));
defparam
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = MEM_DEPTH, // MEM_DEPTH = (2**IDX_SIZE);
altera_syncram_component.operation_mode = "SINGLE_PORT",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_a = "UNREGISTERED",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_port_a = "DONT_CARE",
altera_syncram_component.widthad_a = IDX_SIZE, // address width
altera_syncram_component.width_a = S_BIT; // entire memory line width
endmodule // selector_memory
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/rtl/sr_memory.sv 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// Shift Register Memory Module
// =====================================================================
`include "branch_header.vh"
`timescale 1 ps / 1 ps
import branch_package::*;
module sr_memory(
address,
clock,
data,
rden,
wren,
q);
input [SR_IDX-1:0] address;
input clock;
input [SR_SIZE-1:0] data;
input rden;
input wren;
output [SR_SIZE-1:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [SR_SIZE-1:0] sub_wire0;
wire [SR_SIZE-1:0] q = sub_wire0[SR_SIZE-1:0];
altera_syncram altera_syncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address2_a (1'b1),
.address2_b (1'b1),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccencbypass (1'b0),
.eccencparity (8'b0),
.eccstatus ( ),
.q_b ( ),
.rden_b (1'b1),
.sclr (1'b0),
.wren_b (1'b0));
defparam
altera_syncram_component.width_byteena_a = 1,
altera_syncram_component.clock_enable_input_a = "BYPASS",
altera_syncram_component.clock_enable_output_a = "BYPASS",
altera_syncram_component.intended_device_family = "Arria 10",
altera_syncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altera_syncram_component.lpm_type = "altera_syncram",
altera_syncram_component.numwords_a = N, // MEM_DEPTH == # of shift registers
altera_syncram_component.operation_mode = "SINGLE_PORT",
altera_syncram_component.outdata_aclr_a = "NONE",
altera_syncram_component.outdata_sclr_a = "NONE",
altera_syncram_component.outdata_reg_a = "UNREGISTERED",
altera_syncram_component.power_up_uninitialized = "FALSE",
altera_syncram_component.read_during_write_mode_port_a = "DONT_CARE",
altera_syncram_component.widthad_a = SR_IDX, // address width
altera_syncram_component.width_a = SR_SIZE; // entire memory line width
endmodule // sr_memory
\ No newline at end of file
The_Full_State_Simulator_(BP_and_Cache)/hw/sim/setup_ase 0 → 100644
#!/bin/sh
##
## Setup ASE environment using ../rtl/sources.txt.
##
# Absolute path to this script
SCRIPT=$(readlink -f "$0")
SCRIPT_PATH=$(dirname "$SCRIPT")
afu_sim_setup --sources="${SCRIPT_PATH}/../rtl/sources.txt" $@
The_Full_State_Simulator_(BP_and_Cache)/sw/10000000_cache_int32_trace.txt.zip 0 → 100644
The file could not be displayed because it is too large.
The_Full_State_Simulator_(BP_and_Cache)/sw/2nd_bench_80274735_int64_trace.txt.zip 0 → 100644
The file could not be displayed because it is too large.
The_Full_State_Simulator_(BP_and_Cache)/sw/Makefile 0 → 100644
include common_include.mk
# Primary test name
TEST = full_system
# Build directory
OBJDIR = obj
CFLAGS += -I./$(OBJDIR) -std=c11
CPPFLAGS += -I./$(OBJDIR)
# Files and folders
SRCS = $(TEST).c
OBJS = $(addprefix $(OBJDIR)/,$(patsubst %.c,%.o,$(SRCS)))
# Targets (build only $(TEST)_ase by default)
all: $(TEST) $(TEST)_ase
# AFU info from JSON file, including AFU UUID
AFU_JSON_INFO = $(OBJDIR)/afu_json_info.h
$(AFU_JSON_INFO): ../hw/rtl/$(TEST).json | objdir
afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
$(OBJS): $(AFU_JSON_INFO)
$(TEST): $(OBJS)
$(CC) -o $@ $^ $(LDFLAGS) $(FPGA_LIBS)
$(TEST)_ase: $(OBJS)
$(CC) -o $@ $^ $(LDFLAGS) $(ASE_LIBS)
$(OBJDIR)/%.o: %.c | objdir
$(CC) $(CFLAGS) -c $< -o $@
clean:
rm -rf $(TEST) $(TEST)_ase $(OBJDIR)
objdir:
@mkdir -p $(OBJDIR)
.PHONY: all clean
The_Full_State_Simulator_(BP_and_Cache)/sw/common_include.mk 0 → 100644
##
## Common sw build rules
##
COPT ?= -g -O2
CPPFLAGS ?= -std=c++11
CXX ?= g++
LDFLAGS ?=
ifeq (,$(CFLAGS))
CFLAGS = $(COPT)
endif
ifneq (,$(ndebug))
else
CPPFLAGS += -DENABLE_DEBUG=1
endif
ifneq (,$(nassert))
else
CPPFLAGS += -DENABLE_ASSERT=1
endif
# stack execution protection
LDFLAGS +=-z noexecstack
# data relocation and projection
LDFLAGS +=-z relro -z now
# stack buffer overrun detection
# Note that CentOS 7 has gcc 4.8 by default. When we switch
# to a system with gcc 4.9 or newer this should be changed to
# CFLAGS="-fstack-protector-strong"
CFLAGS +=-fstack-protector
# Position independent execution
CFLAGS +=-fPIE -fPIC
LDFLAGS +=-pie
# fortify source
CFLAGS +=-D_FORTIFY_SOURCE=2
# format string vulnerabilities
CFLAGS +=-Wformat -Wformat-security
ifeq (,$(DESTDIR))
ifneq (,$(prefix))
CPPFLAGS += -I$(prefix)/include
LDFLAGS += -L$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(prefix)/lib \
-L$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(prefix)/lib64
endif
else
ifeq (,$(prefix))
prefix = /usr/local
endif
CPPFLAGS += -I$(DESTDIR)$(prefix)/include
LDFLAGS += -L$(DESTDIR)$(prefix)/lib -Wl,-rpath-link -Wl,$(prefix)/lib -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib \
-L$(DESTDIR)$(prefix)/lib64 -Wl,-rpath-link -Wl,$(prefix)/lib64 -Wl,-rpath -Wl,$(DESTDIR)$(prefix)/lib64
endif
LDFLAGS += -luuid
FPGA_LIBS = -lopae-c
ASE_LIBS = -lopae-c-ase
The_Full_State_Simulator_(BP_and_Cache)/sw/int32_cache_trace_converter.c 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// converting trace file to lines of 32-bit ints
// =====================================================================
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
int main(int argc, char const *argv[])
{
int size= atoi(argv[1]);
int i,j,k;
char c1;
char *code;
code = (char *)malloc(33);
int *trline;
trline = (int *)malloc(4*size);
// long long int *trline_int64;
// trline_int64 = (long long int *)malloc(8*size);
FILE* file = fopen("cache_trace.txt", "r");
for (i = 0; i < size; ++i)
{
// initialize the trace-line 32-bit integer
trline[i]=0;
// read 64 characters from a single trace-line
for (k = 0; k < 32; ++k)
{
if (k<4)
{
code[k] = '0';
}
else
{
code[k] = (char)fgetc(file);
}
}
code[32]='\0';
// printf("string -->%s\n", code);
// 3rd step: fake-read the last charachter '\0' of each text-line
c1 = (char)fgetc(file);
// convert 32 chars to 32-bit integer
trline[i] = strtoll(code, NULL, 2);
}
fclose(file);
// mode = w : Creates an empty file for writing
FILE* newf = fopen("10000000_cache_int32_trace.txt", "w");
for (i = 0; i < size; ++i)
{
fprintf(newf, "%d\n", trline[i]);
}
fclose(newf);
free(trline);
free(code);
return 0;
}
The_Full_State_Simulator_(BP_and_Cache)/sw/int64_bp_trace_converter.c 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// converting trace file to lines of 64bit ints
// =====================================================================
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
int main(int argc, char const *argv[])
{
int size= atoi(argv[1]);
int i,j,k;
char c1;
char *code;
code = (char *)malloc(65);
long long int *trline;
trline = (long long int *)malloc(8*size);
// long long int *trline_int64;
// trline_int64 = (long long int *)malloc(8*size);
FILE* file = fopen("branch_trace.txt", "r");
for (i = 0; i < size; ++i)
{
// initialize the trace-line 64-bit integer
trline[i]=0;
// 1st step: fake-read the unnecessary bits
for (j = 0; j < 6; ++j)
{
c1 = (char)fgetc(file);
}
// 2nd step: read 64 characters from a single trace-line
for (k = 0; k < 64; ++k)
{
code[k] = (char)fgetc(file);
}
code[64]='\0';
// printf("string -->%s\n", code);
// 3rd step: fake-read the last charachter '\0' of each text-line
c1 = (char)fgetc(file);
// convert 64 chars to 64bit integer
trline[i] = strtoll(code, NULL, 2);
// printf("64bit ---> %lld\n", trline[i]);
}
fclose(file);
// mode = w : Creates an empty file for writing
FILE* newf = fopen("2nd_bench_80274735_int64_trace.txt", "w");
for (i = 0; i < size; ++i)
{
fprintf(newf, "%lld\n", trline[i]);
}
fclose(newf);
// // FILE* int64 = fopen("int64_trace.txt", "r");
// // for (i = 0; i < size; ++i)
// // {
// // fscanf(int64,"%lld",&trline_int64[i]);
// // printf("64bit read---> %lld\n", trline_int64[i]);
// // }
// // fclose(int64);
// free(trline_int64);
free(trline);
free(code);
return 0;
}
The_Full_State_Simulator_(BP_and_Cache)/sw/obj/afu_json_info.h 0 → 100644
//
// Generated by afu_json_mgr from ../hw/rtl/predictor.json
//
#ifndef __AFU_JSON_INFO__
#define __AFU_JSON_INFO__
#define AFU_ACCEL_NAME "nbit"
#define AFU_ACCEL_UUID "4634522F-0D1F-4FD3-983F-8FB7C50B552D"
#define AFU_IMAGE_INTERFACE_UUID "00000000-0000-0000-0000-000000000000"
#define AFU_IMAGE_MAGIC_NO 488605312
#define AFU_IMAGE_POWER 0
#define AFU_TOP_IFC "ccip_std_afu"
#endif // __AFU_JSON_INFO__
The_Full_State_Simulator_(BP_and_Cache)/sw/read_from_txt_char_to_64bitint.c 0 → 100644
// =====================================================================
// Konstantinos Kyriakidis,
// Electrical and Computer Engineering, Technical University of Crete,
// kkyriakidis@mhl.tuc.gr
//
// read char lines from .txt directly to 64-bit ints
// =====================================================================
#include <stdint.h>
#include <stdio.h>
int main(int argc, char *argv[])
{
char c1,c2,c3,c4;
char *buffer = malloc(65); // 64 bits +1 for the '\0'
int i,j,k,m;
// trace file size / number of trace-lines
int trace_size = atoi(argv[1]);
// trace-line length
int trace_line_length = atoi(argv[2]);
// number of unnecessary bits
int unnecessary_bits = trace_line_length - 64;
// Dynamic size allocation for the trace-table (TT)
FILE *file;
// buffer for charachters raed from file
char *code = malloc(trace_size*64);
// buffer for 64-bit integers
long long int *trline = malloc(trace_size*64);
file = fopen("branch_trace.txt", "r");
for (i = 0; i < trace_size; ++i)
{
// 1st step: fake-read the unnecessary bits
for (j = 0; j < 6; ++j)
{
c1 = (char)fgetc(file);
}
// 2nd step: read 64 characters from a single trace-line
for (k = 0; k < 64; ++k)
{
code[i*64+k] = (char)fgetc(file);
}
// 3rd step: fake-read the last charachter of each line
c1 = (char)fgetc(file);
}
fclose(file);
// print read trace-lines
for (i = 0; i < trace_size*64; ++i)
{
if (i!=0 & i%64==0)
{
printf("\n");
}
printf("%c", code[i]);
}
// newline after final trace-line read.....
printf("\n");
// convert 64 chars to a buffer string
for (i = 0; i < trace_size; ++i)
{
trline[i]=0;
// 1st step : create 64 char string
for (k = 0; k < 64; ++k)
{
buffer[k]= code[i*64+k];
}
buffer[64]='\0';
// printf("%s\n", buffer);
// 2nd step : convert string to a single 64-bit integer
while (*buffer)
{
trline[i] *= 2;
if (*buffer++ == '1')
{
trline[i] += 1;
}
}
}
// print 64-bit integers for debugging
for (i = 0; i < trace_size; ++i)
{
printf("%lld\n",trline[i]);
}
return 0;
}
The_Full_State_Simulator_(BP_and_Cache)/sw/sim_log.txt 0 → 100644
This diff could not be displayed because it is too large.
The_Full_State_Simulator_(BP_and_Cache)/sw/sw.sh 0 → 100755
# =====================================================================
# Konstantinos Kyriakidis,
# Electrical and Computer Engineering, Technical University of Crete,
# kkyriakidis@mhl.tuc.gr
#
# -- SW execution bash script --
# =====================================================================
#!/bin/bash
export ASE_WORKDIR=/home/gpekridis/0_full_system/hw/build_sim/work
make
# ./full_system_ase 1000000 8192 70 1000000
# ./full_system_ase 2000 256 70 10000000
# ---------------- parameters ---------------------------------
# 1. BP_trace_size
# 2. BP_input_buffer_size
# 3. BP_trace_line_lenght
# 4. Cache_trace_size
# 5. SIZE (cache depth parameter)
# 6. MEM_DEPTH (BHT and BTB depth parameter)
# 7. # of history registers
# 8. PHT_MEM_DEPTH (number of words in the PHT)
./full_system_ase 1000 256 1000 32 1024 4 1024
\ No newline at end of file
ug101_HARP_Intro_Guide.pdf 0 → 100644
No preview for this file type
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