Update README.md

README.md

@@ -19,7 +19,16 @@ This document provides instructions on how to execute the provided FPGA-accelera
 
 
 <a name="overview"></a>
-# Overview
+# EDRA Demonstration Application Overview
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+The application developed as a demonstrator for EDRA is based on the [RAxML application](https://github.com/stamatak/standard-RAxML). The application has been modified according to the Decoupled Access Execute paradigm developed within the EDRA project and an FPGA accelerator has been developed to perform the most demanding computational task. The FPGA-accelerated application is designed to be deployed on an Amazon F1 instance and for demonstration purposes it includes a small data set as well as a software component that is meant to verify that the results obtained be the original application and the accelerated one are equivalent.
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+The accelerated application is provided in a binary form. The software components are the compiled source code running on the host processor and the FPGA accelerator is in the form of an AWS-compatible binary file containing the FPGA bitstream and all other components required to execute the application. A small dataset is also provided for a sample run. Source code for the software application and the accelerator can be provided upon request.
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+To execute the accelerated application
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 * SDAccel is a complete development environment for applications accelerated using Xilinx FPGAs
 * It leverages the OpenCL heterogeneous computing framework to offload compute intensive workloads to the FPGA
 * The accelerated application is written in  C/C++, OpenCL or RTL with OpenCL APIs